PLL Circuit Design Engineer

Key Areas of Responsibility

1.           Analog PLL / All digital PLL design at TSMC advance process node

2.           Mixed mode design flow at advanced process.

3.           Device benchmark from PLL circuit point of view




1.           Minimum of master degree majoring in EE. Higher degree is preferred.

2.           Familiar with basic PLL theory and using Matlab codes to model PLL.

3.           Familiar with Spread-Spectrum-Clocks.

4.           Have designed (analog, or all-digital) PLLs


The following are preferred but not required

1.           Have done measurements, and/or designs of PCBs.

2.           Design experiences in phase-noise BIST circuits

3.           Experiences in PLL layout constraints and floor-planning

4.           Experiences above 10GHz LC-tank PLLs

5.           Digital design experiences (Verilog & APR)


Languages:         Capable of very effective communications in oral and written English


Key Experience:

1.           Preferable with above 5 years of working experience.

2.           Additional experience in device/integration/product engineering would be advantageous.


Personal Attributes:       

1.           Proactive and willing to take challenges.

2.           Highly self-motivated to learn new things and build new skills

3.           Strong in project management, communication, and organizing information




All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.

Date:  Jul 1, 2024
Country/Region:  JP
City:  Yokohama
Company:  TSMC Design Tech. Japan, Inc.