Design Verification Engineer

Job Description

• Verify TSMC’s product like ARM processor based SOC and memory subsystem test chips
• Develop verification methodology and implement test bench components using System Verilog, UVM, and low power verification
• Develop comprehensive test plan and implement test cases to verify different test chips
• Work closely with Design and DFT teams to develop/verify various functional/DFT tests
• Write functional cover groups and cover points for coverage closure. Perform RTL code coverage, System Verilog Assertion coverage, System Verilog functional coverage
• Drive and adopt new verification methodologies and flows for efficiency improvements.



• BCH and above in EE, CS related fields with 3-15 years of hands-on experience
• Strong problem solving, debugging and programming skills (Python/TCL/C++)
• Strong hands-on experience with architecting and developing IP/SoC level reusable verification environments using SystemVerilog UVM methodologies.
• Hands-on experience developing testbench and testcases in System Verilog
• Knowledge in Constrained Random and Coverage Driven testbench  
• Gate Level Simulation experience
• Proficiency in English is a must"




All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.

Date:  Jul 9, 2024
Country/Region:  JP
City:  Yokohama or Osaka
Company:  TSMC Design Tech. Japan, Inc.